1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although it is common to reduce (refine) the dimension for each device for increased memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, the costs of lithography process are ever increasing. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. That is, it is likely that difficulties would be encountered in device operation itself.
Therefore, a large number of semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, for example, Japanese Patent Laid-Open No. 2007-266143; U.S. Pat. No. 5,599,724; and U.S. Pat. No. 5,707,885).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a cylinder-type structure. Those semiconductor storage devices using transistors with the cylinder-type structure are provided with multiple conductive layers corresponding to gate electrodes and pillar-like columnar semiconductors. Each of the columnar semiconductors serves as a channel (body) part of each of the transistors. Memory gate insulation layers are provided around the columnar semiconductors. Such a configuration including these conductive layers, columnar semiconductors, and memory gate insulation layers is referred to as a “memory string”.
For three-dimensional memory with pillar-like columnar semiconductors as disclosed in the patent documents mentioned above, for example, although bit lines can be formed on the top surface of the lamination structure, source lines should be formed on the bottom surface of the lamination structure, and their contacts should also be formed with trenches dug down to the bottom surface of the lamination structure. In general, source lines are highly doped with impurities for lowering resistance. To mitigate thermal diffusion of impurities from the source lines while keeping good contact resistance with such source lines, sensitive interface control is required for different thermal processes.
In this respect, such a three-dimensional type non-volatile semiconductor storage device has been disclosed in, e.g., Japanese Patent Laid-Open No. 2007-317874, where memory strings are formed in U-shape, enabling both bit lines and source lines to be formed on the surface of the lamination structure.
However, Japanese Patent Laid-Open No. 2007-317874 requires word lines to be formed separately for each memory string, which poses a problem that the wiring resistance of the word lines cannot be reduced.